82371AB Datasheet, PDF (43/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

E
82371AB (PIIX4)
3.1.1. PCI CONFIGURATION REGISTERS (FUNCTION 0)
Table 4. PCI Configuration Registers—Function 0 (PCI to ISA Bridge)
Offset Address Mnemonic
Register Name
00–01h
VID
Vendor Identification
02–03h
DID
Device Identification
04–05h
PCICMD
PCI Command
06–07h
PCISTS
PCI Device Status
08h
RID
Revision Identification
09−0Bh
CLASSC
Class Code
0C–0Dh
—
Reserved
0Eh
HEDT
Header Type
0F–4Bh
—
Reserved
4Ch
IOR
ISA I/O Recovery Timer
4Dh
—
Reserved
4E–4Fh
XBCS
X-Bus Chip Select
50–5Fh
—
Reserved
60–63h
PIRQRC[A:D] PIRQx Route Control
64h
SERIRQC
Serial IRQ Control
65–68h
—
Reserved
69h
TOM
Top of Memory
6A–6Bh
MSTAT
Miscellaneous Status
6C–75h
—
Reserved
76–77h
MBDMA[1:0] Motherboard Device DMA Control
78–7Fh
—
Reserved
80h
APICBASE APIC Base Address Relocation
81h
—
Reserved
82h
DLC
Deterministic Latency Control
83–8Fh
—
Reserved
90−91h
92−95h
96−AFh
B0−B3h
B4−CAh
CBh
PDMACFG
DDMABASE
—
GENCFG
—
RTCCFG
PCI DMA Configuration
Distributed DMA Slave Base Pointer
Reserved
General Configuration
Reserved
Real Time Clock Configuration
CC–FFh
—
Reserved
Access
RO
RO
R/W
R/W
RO
RO
—
RO
—
R/W
—
R/W
—
R/W
R/W
—
R/W
R/W
—
R/W
—
R/W
—
R/W
—
R/W
R/W
—
R/W
—
R/W
—
PRELIMINARY
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4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)