82371AB Datasheet, PDF (229/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

E
82371AB (PIIX4)
Table 34. Different Power Management Modes Supported (Standard System Model)
PM Mode
System Strategy
System Target
Power
System Target
Resume Latency
Global Standby
All monitored devices are powered off, and the Variable
processor’s clock is stopped.
Variable
Powered-on
Same as Global Standby, but power is
Suspend (POS) removed from the clock generators.
<250 mW
~20 ms
Suspend to RAM
(STR)
Power is removed everywhere in the system
except: power management section of PIIX4,
slow refresh logic in the memory controller and
graphics chips, and the graphics and DRAM
memory.
<20 mW
~1 sec
Suspend to Disk/ Power is removed everywhere except the
Soft Off
power management sections of PIIX4.
(STD/Soff)
<300 uW
< 30 sec
PIIX4 controls the system entering the various suspend states through the suspend control signals listed in
Table 35. Upon initiation of suspend, PIIX4 will assert the SUS_STAT[1:2]#, SUSA#, SUSB#, and SUSC#
signals in a well defined sequence to switch the system into the desired power state. The SUSA#, SUSB#, and
SUSC# signals can be used to control various power planes in the system. The SUS_STAT1# signal is a status
signal that indicates to the host bridge when to enter or exit a suspend state, or when to enter or exit a stop clock
state (when the system is still running). This is typically used to place the DRAM controller into a Suspend
Refresh mode of operation. The SUS_STAT2# signal is a status signal that can be used to indicate to other
system devices when to enter or exit a suspend state (like the graphics and Cardbus controllers). See “System
Suspend And Resume Control Signaling” section for sequencing details. Note that these signals are associated
with a particular type of suspend mode and power plane for descriptive purposes in this section. The system
designer can, however, use these signals to control any type of function desired.
The system is placed in a suspend mode by programming the Power Management Control register. The
Suspend Type is first programmed and then the Suspend Enable bit is set. This causes PIIX4 to automatically
sequence into the programmed suspend mode.
PRELIMINARY
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