82371AB Datasheet, PDF (203/284 Pages) Intel Corporation – PCI-TO-ISA / IDE XCELERATOR PIIX4

E
82371AB (PIIX4)
by setting [CC_EN] bit along with other optional control bits. Table 32 details register bit settings required to
place the PIIX4 clock control into the various modes of operation. Figure 11 and Figure 12 give examples of
various clock control conditions.
• Primary Mechanisms
• Stop Grant or Quick Start
• Sleep
• Stop Clock
• Deep Sleep
• Variations
• Manual Throttle
• Thermal Throttle
• Stop Break and Burst Execution
HCLK
STPCLK#, SLP#
L2 Cache
SRAM
Tag
HCLK
CPU
Host-to-PCI
Bridge
PCLK
Main Memory
DRAM
CLKRUN#
PCI Bus
PCLK
SUSCLK
System PLL
STP_CPU#
STP_PCI#
SUSA#
PIIX4
SUSA#
clk_cntr
Figure 10. Clock Control
PRELIMINARY
203
4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)