MC3S12RG128 Datasheet, PDF (99/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

2.3.2.6.2
Chapter 2 Port Integration Module (PIM3RG128V1) Block Description
Port H Input Register (PTIH)
Module Base + 0x_0021
R
W
Reset
7
PTIH7
—
6
PTIH6
5
PTIH5
4
PTIH4
3
PTIH3
2
PTIH2
—
—
—
—
—
= Unimplemented or Reserved
Figure 2-33. Port H Input Register (PTIH)
1
PTIH1
—
0
PTIH0
—
Read: Anytime.
Write: Never, writes to this register have no effect.
This register always reads back the status of the associated pins. This can also be used to detect overload
or short circuit conditions on output pins.
2.3.2.6.3 Port H Data Direction Register (DDRH)
Module Base + 0x_0022
R
W
Reset
7
DDRH7
0
6
DDRH6
5
DDRH5
4
DDRH4
3
DDRH3
2
DDRH2
0
0
0
0
0
Figure 2-34. Port H Data Direction Register (DDRH)
Read: Anytime.
Write: Anytime.
This register configures each port H pin as either input or output.
Table 2-29. DDRH Field Descriptions
1
DDRH1
0
0
DDRH0
0
Field
Description
7–0
DDRH[7:0]
Data Direction Port H Bits
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to two bus cycles until the correct value is read on
PTH or PTIH registers, when changing the DDRH register.
MC3S12RG128 Data Sheet, Rev. 1.05
Freescale Semiconductor
99