MC3S12RG128 Datasheet, PDF (294/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
Depending on the TIOS bit for the corresponding channel, these registers are used to latch the value of the
free-running counter when a defined transition is sensed by the corresponding input capture edge detector
or to trigger an output action for output compare.
Read anytime. Write anytime for output compare function. Writes to these registers have no meaning or
effect during input capture. All timer input capture/output compare registers are reset to 0x0000.
10.3.2.15 16-Bit Pulse Accumulator A Control Register (PACTL)
Module Base + 0x0020
7
R
0
W
6
5
4
3
2
1
0
PAEN
PAMOD
PEDGE
CLK1
CLK0
PAOVI
PAI
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 10-17. 16-Bit Pulse Accumulator Control Register (PACTL)
16-Bit Pulse Accumulator A (PACA) is formed by cascading the 8-bit pulse accumulators PAC3 and
PAC2.
When PAEN is set, the PACA is enabled. The PACA shares the input pin with IC7.
Read: Anytime
Write: Anytime
Table 10-14. PACTL Field Descriptions
Field
6
PAEN
5
PAMOD
Description
Pulse Accumulator A System Enable — PAEN is independent from TEN. With timer disabled, the pulse
accumulator can still function unless pulse accumulator is disabled.
0 16-Bit Pulse Accumulator A system disabled. 8-bit PAC3 and PAC2 can be enabled when their related enable
bits in ICPAR (0x0028) are set. Pulse Accumulator Input Edge Flag (PAIF) function is disabled.
1 16-Bit Pulse Accumulator A system enabled. The two 8-bit pulse accumulators PAC3 and PAC2 are cascaded
to form the PACA 16-bit pulse accumulator. When PACA in enabled, the PACN3 and PACN2 registers contents
are respectively the high and low byte of the PACA. PA3EN and PA2EN control bits in ICPAR (0x0028) have
no effect. Pulse Accumulator Input Edge Flag (PAIF) function is enabled.
Pulse Accumulator Mode — This bit is active only when the Pulse Accumulator A is enabled (PAEN = 1).
0 Event counter mode
1 Gated time accumulation mode
MC3S12RG128 Data Sheet, Rev. 1.05
294
Freescale Semiconductor