MC3S12RG128 Datasheet, PDF (317/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
The pins associated with channels 0-6 become output-tied to OCn (n = 0..6) when
• TEN = 1, IOSn = 1, and either or both of OMn and OLn are set or
• OC7Mn = 1, IOS7 = 1 and IOSn = 1
Once the pin is configured as OC, its initial state is zero and its status is changed (if needed) on consecutive
clock cycles following the write which enabled the ECT to drive the pin. In other words after a pin starts
to be driven by ECT OC logic, it is forced low for at least one clock cycle.
10.5 Reset
The reset state of each individual bit is listed within Section 10.3, “Memory Map and Registers” which
details the registers and their bit-fields.
10.6 Interrupts
This section describes interrupts originated by the ECT16B8C block.The MCU must service the interrupt
requests. Table 10-28 lists the interrupts generated by the ECT to communicate with the MCU.
The ECT only originates interrupt requests. The following is a description of how the module makes a
request and how the MCU should acknowledge that request. The interrupt vector offset and interrupt
number are chip dependent.
Table 10-28. ECT Interrupts
Interrupt Source
Timer channel 7–0
Modulus counter underflow
Pulse accumulator B overflow
Pulse accumulator A input
Pulse accumulator A overflow
Timer overflow
Description
Active high timer channel interrupts 7–0
Active high modulus counter interrupt
Active high pulse accumulator B interrupt
Active high pulse accumulator A input interrupt
Pulse accumulator overflow interrupt
Timer overflow interrupt
10.6.1 Channel [7:0] Interrupt
This active high output will be asserted by the module to request a timer channel 7 - 0 interrupt to be
serviced by the system controller.
10.6.2 Modulus Counter Interrupt
This active high output will be asserted by the module to request a modulus counter underflow interrupt to
be serviced by the system controller.
10.6.3 Pulse Accumulator B Overflow Interrupt)
This active high output will be asserted by the module to request a timer pulse accumulator B overflow
interrupt to be serviced by the system controller.
MC3S12RG128 Data Sheet, Rev. 1.05
Freescale Semiconductor
317