MC3S12RG128 Datasheet, PDF (413/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 14 Pulse-Width Modulator (PWM8B8CV1)
14.3.2.5 PWM Center Align Enable Register (PWMCAE)
The PWMCAE register contains eight control bits for the selection of center aligned outputs or left aligned
outputs for each PWM channel. If the CAEx bit is set to a one, the corresponding PWM output will be
center aligned. If the CAEx bit is cleared, the corresponding PWM output will be left aligned. See
Section 14.4.2.5, “Left Aligned Outputs” and Section 14.4.2.6, “Center Aligned Outputs” for a more
detailed description of the PWM output modes.
Module Base + 0x0004
R
W
Reset
7
CAE7
0
6
CAE6
5
CAE5
4
CAE4
3
CAE3
2
CAE2
1
CAE1
0
0
0
0
0
0
Figure 14-7. PWM Center Align Enable Register (PWMCAE)
Read: Anytime
Write: Anytime
NOTE
Write these bits only when the corresponding channel is disabled.
Table 14-7. PWMCAE Field Descriptions
0
CAE0
0
Field
7–0
CAE[7:0]
Description
Center Aligned Output Modes on Channels 7–0
0 Channels 7–0 operate in left aligned output mode.
1 Channels 7–0 operate in center aligned output mode.
14.3.2.6 PWM Control Register (PWMCTL)
The PWMCTL register provides for various control of the PWM module.
Module Base + 0x0005
7
6
5
4
3
2
1
0
R
0
0
CON67
CON45
CON23
CON01
PSWAI
PFRZ
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 14-8. PWM Control Register (PWMCTL)
Read: Anytime
Write: Anytime
There are three control bits for concatenation, each of which is used to concatenate a pair of PWM
channels into one 16-bit channel. When channels 6 and 7are concatenated, channel 6 registers become the
high order bytes of the double byte channel. When channels 4 and 5 are concatenated, channel 4 registers
become the high order bytes of the double byte channel. When channels 2 and 3 are concatenated, channel
MC3S12RG128 Data Sheet, Rev. 1.05
Freescale Semiconductor
413