MC3S12RG128 Datasheet, PDF (90/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 2 Port Integration Module (PIM3RG128V1) Block Description
2.3.2.3.3 Port M Data Direction Register (DDRM)
Module Base + 0x_0012
R
W
Reset
7
DDRM7
0
6
DDRM6
5
DDRM5
4
DDRM4
3
DDRM3
2
DDRM2
0
0
0
0
0
Figure 2-18. Port M Data Direction Register (DDRM)
1
DDRM1
0
0
DDRM0
0
Read: Anytime.
Write: Anytime.
This register configures each port M pin as either input or output.
• The CAN forces the I/O state to be an output for each port line associated with an enabled output
(TXCAN0). It also forces the I/O state to be an input for each port line associated with an enabled
input (RXCAN0). In those cases the data direction bits will not change.
• The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral
module is disabled.
Table 2-13. DDRM Field Descriptions
Field
Description
7–0
DDRM[7:0]
Data Direction Port M Bits
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to two bus cycles until the correct value is read on
PTM or PTIM registers, when changing the DDRM register.
MC3S12RG128 Data Sheet, Rev. 1.05
90
Freescale Semiconductor