MC3S12RG128 Datasheet, PDF (233/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 8 Analog-to-Digital Converter (ATD10B8CV3)
8.3.2.11 ATD Input Enable Register (ATDDIEN)
Module Base + 0x000D
R
W
Reset
7
IEN7
0
Read: Anytime
6
IEN6
5
IEN5
4
IEN4
3
IEN3
2
IEN2
0
0
0
0
0
Figure 8-13. ATD Input Enable Register (ATDDIEN)
1
IEN1
0
0
IEN0
0
Write: Anytime
Table 8-21. ATDDIEN Field Descriptions
Field
7–0
IEN[7:0]
Description
ATD Digital Input Enable on channel x (x = 7, 6, 5, 4, 3, 2, 1, 0) — This bit controls the digital input buffer from
the analog input pin (ANx) to PTADx data register.
0 Disable digital input buffer to PTADx
1 Enable digital input buffer to PTADx.
Note: Setting this bit will enable the corresponding digital input buffer continuously. If this bit is set while
simultaneously using it as an analog port, there is potentially increased power consumption because the
digital input buffer maybe in the linear region.
8.3.2.12 Port Data Register (PORTAD)
The data port associated with the ATD can be configured as general-purpose I/O or input only, as specified
in the device overview. The port pins are shared with the analog A/D inputs AN7–0.
Module Base + 0x000F
R
W
Reset
Pin
Function
7
PTAD7
1
AN7
Read: Anytime
6
PTAD6
5
PTAD5
4
PTAD4
3
PTAD3
2
PTAD2
1
1
1
1
1
AN6
AN5
AN4
AN3
AN2
= Unimplemented or Reserved
Figure 8-14. Port Data Register (PORTAD)
Write: Anytime, no effect
The A/D input channels may be used for general purpose digital input.
1
PTAD1
1
AN1
0
PTAD0
1
AN0
MC3S12RG128 Data Sheet, Rev. 1.05
Freescale Semiconductor
233