MC3S12RG128 Datasheet, PDF (103/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

2.3.2.7 Port J Registers
Chapter 2 Port Integration Module (PIM3RG128V1) Block Description
2.3.2.7.1 Port J I/O Register (PTJ)
Module Base + 0x_0028
7
6
5
4
3
2
R
0
0
0
0
PTJ7
PTJ6
W
CAN4 TXCAN4 RXCAN4
IIC SCL
SDA
CAN0 TXCAN0 RXCAN0
Reset
0
0
—
—
—
—
= Unimplemented or Reserved
Figure 2-40. Port J I/O Register (PTJ)
1
PTJ1
0
PTJ0
0
0
Read: Anytime.
Write: Anytime.
If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port register,
otherwise the value at the pins is read.
Table 2-35. PTJ Field Descriptions
Field
7–6
PJ[7:6]
Description
PJ7–PJ6
• The CAN4 function (TXCAN4 and RXCAN4) takes precedence over the IIC, the CAN0 and the general
purpose I/O function if the CAN4 module is enabled.
• The IIC function (SCL and SDA) takes precedence over CAN0 and the general purpose I/O function if the IIC
is enabled. If the IIC module takes precedence the SDA and SCL outputs are configured as open drain
outputs. Refer to IIC Block Guide for details.
• The CAN0 function (TXCAN0 and RXCAN0) takes precedence over the general purpose I/O function if the
CAN0 module is enabled.Refer to MSCAN Block Guide for details.
MC3S12RG128 Data Sheet, Rev. 1.05
Freescale Semiconductor
103