MC3S12RG128 Datasheet, PDF (348/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 12 Freescale’s Scalable Controller Area Network (MSCANV2)
Register
Name
Bit 7
6
5
4
3
2
1
0x0010–0x0013 R
CANIDAR0–3 _W ^AC7
AC6
AC5
AC4
AC3
AC2
AC1
0x0014–0x0017 R
CANIDMRx
W
AM7
0x0018–0x001B R
CANIDAR4–7 _W ^AC7
0x001C–0x001F R
CANIDMR4–7 _W
AM7
AM6
AC6
AM6
AM5
AC5
AM5
AM4
AC4
AM4
AM3
AC3
AM3
AM2
AC2
AM2
AM1
AC1
AM1
0x0020–0x002F R
CANRXFG
W
0x0030–0x003F R
CANTXFG
W
See Section 12.3.3, “Programmer’s Model of Message Storage”
See Section 12.3.3, “Programmer’s Model of Message Storage”
= Unimplemented or Reserved
u = Unaffected
Figure 12-3. MSCAN Register Summary (continued)
Bit 0
AC0
AM0
AC0
AM0
12.3.2 Register Descriptions
This section describes in detail all the registers and register bits in the MSCAN module. Each description
includes a standard register diagram with an associated figure number. Details of register bit and field
function follow the register diagrams, in bit order. All bits of all registers in this module are completely
synchronous to internal clocks during a register read.
12.3.2.1 MSCAN Control Register 0 (CANCTL0)
The CANCTL0 register provides various control bits of the MSCAN module as described below.
Module Base + 0x0000
R
W
Reset:
7
RXFRM
0
6
RXACT
5
CSWAI
4
SYNCH
3
TIME
2
WUPE
0
0
0
0
0
= Unimplemented
Figure 12-4. MSCAN Control Register 0 (CANCTL0)
1
SLPRQ
0
0
INITRQ
1
MC3S12RG128 Data Sheet, Rev. 1.05
348
Freescale Semiconductor