MC3S12RG128 Datasheet, PDF (296/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
10.3.2.16 Pulse Accumulator A Flag Register (PAFLG)
Module Base + 0x0021
7
6
5
4
3
2
1
R
0
0
0
0
0
0
PAOVF
W
Reset
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 10-18. Pulse Accumulator A Flag Register (PAFLG)
0
PAIF
0
Read or write anytime. When the TFFCA bit in the TSCR register is set, any access to the PACNT register
will clear all the flags in the PAFLG register.
Table 10-17. PAFLG Field Descriptions
Field
1
PAOVF
0
PAIF
Description
Pulse Accumulator A Overflow Flag — Set when the 16-bit pulse accumulator A overflows from 0xFFFF to
0x0000,or when 8-bit pulse accumulator 3 (PAC3) overflows from 0x00FF to 0x0000.
When PACMX = 1, PAOVF bit can also be set if 8 - bit pulse accumulator 3 (PAC3) reaches 0x00FF followed by
an active edge on PT3.
This bit is cleared automatically by a write to the PAFLG register with bit 1 set.
Pulse Accumulator Input edge Flag — Set when the selected edge is detected at the PT7 input pin. In event
mode the event edge triggers PAIF and in gated time accumulation mode the trailing edge of the gate signal at
the PT7 input pin triggers PAIF.
This bit is cleared by a write to the PAFLG register with bit 0 set.
Any access to the PACN3, PACN2 registers will clear all the flags in this register when TFFCA bit in register
TSCR(0x0006) is set.
MC3S12RG128 Data Sheet, Rev. 1.05
296
Freescale Semiconductor