MC3S12RG128 Datasheet, PDF (136/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 4 Multiplexed External Bus Interface (MEBIV3) Block Description
4.3 Memory Map and Register Definition
A summary of the registers associated with the MEBI sub-block is shown in Figure 4-2. Detailed
descriptions of the registers and bits are given in the subsections that follow. On most chips the registers
are mappable. Therefore, the upper bits may not be all 0s as shown in the table and descriptions.
4.3.1 Module Memory Map
Name
0x0000
PORTA
0x0001
PORTB
0x0002
DDRA
0x0003
DDRB
0x0004
Reserved
0x0005
Reserved
0x0006
Reserved
0x0007
Reserved
0x0008
PORTE
0x0009
DDRE
0x000A
PEAR
0x000B
MODE
0x000C
PUCR
Bit 7
R
Bit 7
W
R
Bit 7
W
R
Bit 7
W
R
Bit 7
W
R
0
W
R
0
W
R
0
W
R
0
W
R
Bit 7
W
R
Bit 7
W
R
NOACCE
W
R
MODC
W
R
PUPKE
W
6
5
4
3
6
5
4
3
6
5
4
3
6
5
4
3
6
5
4
3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
6
5
4
3
0
PIPOE NECLK LSTRE
0
MODB
MODA
IVIS
0
0
0
PUPEE
Figure 4-2. MEBI Register Summary
2
2
2
2
2
0
0
0
0
2
2
RDWE
0
0
1
1
1
1
1
0
0
0
0
1
0
0
EMK
PUPBE
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
0
0
0
0
Bit 0
0
0
EME
PUPAE
MC3S12RG128 Data Sheet, Rev. 1.05
136
Freescale Semiconductor