MC3S12RG128 Datasheet, PDF (147/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

4.3.2.9
Mode Register (MODE)
Chapter 4 Multiplexed External Bus Interface (MEBIV3) Block Description
Module Base + 0x000B
Starting address location affected by INITRG register setting.
7
6
5
4
3
2
1
0
R
0
0
MODC
MODB
MODA
IVIS
EMK
EME
W
Reset
Special Single Chip
0
0
0
0
0
0
0
0
Emulation Expanded
Narrow
0
0
1
0
1
0
1
1
Special Test
0
1
0
0
1
0
0
0
Emulation Expanded
Wide
0
1
1
0
1
0
1
1
Normal Single Chip
1
0
0
0
0
0
0
0
Normal Expanded
Narrow
1
0
1
0
0
0
0
0
Peripheral
1
1
0
0
0
0
0
0
Normal Expanded Wide
1
1
1
0
0
0
0
0
= Unimplemented or Reserved
Figure 4-14. Mode Register (MODE)
Read: Anytime (provided this register is in the map).
Write: Each bit has specific write conditions. Please refer to the descriptions of each bit on the following
pages.
The MODE register is used to establish the operating mode and other miscellaneous functions (i.e.,
internal visibility and emulation of port E and K).
In special peripheral mode, this register is not accessible but it is reset as shown to system configuration
features. Changes to bits in the MODE register are delayed one cycle after the write.
This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these
accesses will be echoed externally.
MC3S12RG128 Data Sheet, Rev. 1.05
Freescale Semiconductor
147