MC3S12RG128 Datasheet, PDF (298/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
10.3.2.18 Pulse Accumulators Count Registers (PACN1/PACN0)
Module Base + 0x0024
7
6
5
4
3
2
1
R
PACNT7(15) PACNT6(14) PACNT5(13) PACNT4(12) PACNT3(11) PACNT2(10) PACNT1(9)
W
0
PACNT0(8)
Reset
0
0
0
0
0
0
0
0
Figure 10-21. Pulse Accumulators Count Register 1 (PACN1)
Module Base + 0x0025
R
W
Reset
7
PACNT7
0
6
PACNT6
5
PACNT5
4
PACNT4
3
PACNT3
2
PACNT2
1
PACNT1
0
0
0
0
0
0
Figure 10-22. Pulse Accumulators Count Register 0 (PACN0)
0
PACNT0
0
Read or write anytime.
The two 8-bit pulse accumulators PAC1 and PAC0 are cascaded to form the PACB 16-bit pulse
accumulator. When PACB in enabled, (PBEN = 1 in PBCTL, 0x0030) the PACN1 and PACN0 registers
contents are respectively the high and low byte of the PACB.
When PACN1 overflows from 0x00FF to 0x0000, the Interrupt flag PBOVF in PBFLG (0x0031) is set.
Full count register access should take place in one clock cycle. A separate read/write for high byte and low
byte will give a different result than accessing them as a word
NOTE
When clocking pulse and write to the registers occurs simultaneously, write
takes priority and the register is not incremented.
10.3.2.19 16-Bit Modulus Down-Counter Control Register (MCCTL)
Module Base + 0x0026
R
W
Reset
7
MCZI
6
MODMC
5
RDMCL
4
0
ICLAT
3
0
FLMC
2
MCEN
1
MCPR1
0
0
0
0
0
0
0
Figure 10-23. 16-Bit Modulus Down-Counter Control Register (MCCTL)
Read or write anytime.
0
MCPR0
0
MC3S12RG128 Data Sheet, Rev. 1.05
298
Freescale Semiconductor