MC3S12RG128 Datasheet, PDF (94/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 2 Port Integration Module (PIM3RG128V1) Block Description
MODRR[3]
1
Table 2-21. CAN4 Routing
MODRR[2]
1
RXCAN4
TXCAN4
Reserved
MODRR[1]
0
0
1
1
Table 2-22. CAN0 Routing
MODRR[0]
0
1
0
1
RXCAN0
PM0
PM2
PM4
PJ6
TXCAN0
PM1
PM3
PM5
PJ7
2.3.2.5 Port P Registers
2.3.2.5.1 Port P I/O Register (PTP)
Module Base + 0x_0018
R
W
PWM
SPI
Reset
7
PTP7
PWM7
SCK2
0
6
PTP6
PWM6
SS2
0
5
PTP5
4
PTP4
3
PTP3
2
PTP2
PWM5
PWM4
PWM3
PWM2
MOSI2
MISO2
SS1
SCK1
0
0
0
0
Figure 2-24. Port P I/O Register (PTP)
1
PTP1
PWM1
MOSI1
0
0
PTP0
PWM0
MISO1
0
Read: Anytime.
Write: Anytime.
If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port register,
otherwise the value at the pins is read.
• The PWM function takes precedence over the general purpose I/O function if the associated PWM
channel is enabled. While channels 6-0 are output only if the respective channel is enabled, channel
7 can be PWM output or input if the shutdown feature is enabled. Refer to PWM Block Guide for
details.
• The SPI function takes precedence over the general purpose I/O function associated with if
enabled. Refer to SPI Block Guide for details.
• If both PWM and SPI are enabled the PWM functionality takes precedence.
MC3S12RG128 Data Sheet, Rev. 1.05
94
Freescale Semiconductor