MC3S12RG128 Datasheet, PDF (301/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
10.3.2.21 Input Control Pulse Accumulators Register (ICPAR)
Module Base + 0x0028
R
W
Reset
7
6
5
4
3
2
1
0
0
0
0
PA3EN
PA2EN
PA1EN
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 10-25. Input Control Pulse Accumulators Register (ICPAR)
0
PA0EN
0
The 8-bit pulse accumulators PAC3 and PAC2 can be enabled only if PAEN in PATCL (0x0020) is cleared.
If PAEN is set, PA3EN and PA2EN have no effect.
The 8-bit pulse accumulators PAC1 and PAC0 can be enabled only if PBEN in PBTCL (0x0030) is cleared.
If PBEN is set, PA1EN and PA0EN have no effect.
Read or write anytime.
Table 10-21. ICPAR Field Descriptions
Field
3–0
8-Bit Pulse Accumulator Enable
PA[3:0]EN 0 8-Bit Pulse Accumulator is disabled.
1 8-Bit Pulse Accumulator is enabled.
Description
MC3S12RG128 Data Sheet, Rev. 1.05
Freescale Semiconductor
301