MC3S12RG128 Datasheet, PDF (288/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
10.3.2.8 Timer Control Register 1/Timer Control Register 2 (TCTL1/TCTL2)
Module Base + 0x0008
7
R
OM7
W
6
OL7
5
OM6
4
OL6
3
OM5
2
OL5
1
OM4
0
OL4
Reset
0
0
0
0
0
0
0
0
Module Base + 0x0009
7
R
OM3
W
6
OL3
5
OM2
4
OL2
3
OM1
2
OL1
1
OM0
0
OL0
Reset
0
0
0
0
0
0
0
0
Figure 10-10. Timer Control Register 1/Timer Control Register 2 (TCTL1/TCTL2))
Read or write anytime.
Table 10-5. TCTL1/TCTL2 Field Descriptions
Field
7–0
OM[7:0]
OL[7:0]
Description
OMn — Output Mode
OLn — Output Level
These eight pairs of control bits are encoded to specify the output action to be taken as a result of a successful
OCn(n varies from 0 to 7) compare. When either OMn or OLn is one, the port associated with OCn becomes an
output tied to OCn when the corresponding IOSn bit of TIOS register is set and TEN bit of TSCR1 register is set.
Refer to the note on Section 10.4.1.4, “Channel Configurations” for more insight. See Table 10-6.
Note: To enable output action by OMn and OLn bits on timer port, the corresponding bit in OC7M should be
cleared.
To operate the 16-bit pulse accumulators A and B (PACA and PACB) independently of input capture or output
compare 7 and 0 respectively the user must set the corresponding bits IOSn = 1, OMn = 0 and OLn = 0. OC7M7
or OC7M0 in the OC7M register must also be cleared.
.
Table 10-6. Compare Result Output Action
OMn
0
0
1
1
OLn
0
1
0
1
Action
Timer disconnected from output pin logic
Toggle OCn output line
Clear OCn output line to zero
Set OCn output line to one
MC3S12RG128 Data Sheet, Rev. 1.05
288
Freescale Semiconductor