MC3S12RG128 Datasheet, PDF (84/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 2 Port Integration Module (PIM3RG128V1) Block Description
2.3.2.2 Port S Registers
2.3.2.2.1 Port S I/O Register (PTS)
Module Base + 0x_0008
R
W
Reset
7
PTS7
SS0
0
6
PTS6
SCK0
0
5
PTS5
4
PTS4
3
PTS3
2
PTS2
MOSI0
MISO0
TXD1
RXD1
0
0
0
0
Figure 2-9. Port S I/O Register (PTS)
1
PTS1
TXD0
0
0
PTS0
RXD0
0
Read: Anytime.
Write: Anytime.
If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port register,
otherwise the value at the pins is read.
• The SPI pins (PS[7:4]) configuration is determined by several status bits in the SPI module. Refer
to SPI Block Guide for details.
• The SCI ports associated with transmit pins 3 and 1 are configured as outputs if the transmitter is
enabled.
• The SCI ports associated with receive pins 2 and 0 are configured as inputs if the receiver is
enabled. Refer to SCI Block Guide for details.
2.3.2.2.2 Port S Input Register (PTIS)
Module Base + 0x_0009
R
W
Reset
7
PTIS7
—
6
PTIS6
5
PTIS5
4
PTIS4
3
PTIS3
2
PTIS2
—
—
—
—
—
= Unimplemented or Reserved
Figure 2-10. Port S Input Register (PTIS)
1
PTIS1
—
0
PTIS0
—
Read: Anytime.
Write: Never, writes to this register have no effect.
This register always reads back the status of the associated pins. This also can be used to detect overload
or short circuit conditions on output pins.
MC3S12RG128 Data Sheet, Rev. 1.05
84
Freescale Semiconductor