MC3S12RG128 Datasheet, PDF (104/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 2 Port Integration Module (PIM3RG128V1) Block Description
2.3.2.7.2 Port J Input Register (PTIJ)
Module Base + 0x_0029
R
W
Reset
7
PTIJ7
—
6
5
4
3
2
PTIJ6
0
0
0
0
—
—
—
—
—
= Unimplemented or Reserved
Figure 2-41. Port J Input Register (PTIJ)
1
PTIJ1
—
0
PTIJ0
—
Read: Anytime.
Write: Never, writes to this register have no effect.
This register always reads back the status of the associated pins. This can be used to detect overload or
short circuit conditions on output pins.
2.3.2.7.3 Port J Data Direction Register (DDRJ)
Module Base + 0x_002A
R
W
Reset
7
DDRJ7
0
6
5
4
3
2
0
0
0
0
DDRJ6
0
—
—
—
—
= Unimplemented or Reserved
Figure 2-42. Port J Data Direction Register (DDRJ))
1
DDRJ1
0
0
DDRJ0
0
Read: Anytime.
Write: Anytime.
This register configures each port J pin as either input or output.
The CAN forces the I/O state to be an output on PJ7 (TXCAN4) and an input on pin PJ6 (RXCAN4). The
IIC takes control of the I/O if enabled. In these cases the data direction bits will not change. The DDRJ
bits revert to controlling the I/O direction of a pin when the associated peripheral module is disabled.
Table 2-36. DDRJ Field Descriptions
Field
Description
7, 6, 1, 0
DDRJ[7:6]
DDRJ[1:0}
Data Direction Port J Bits
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to two bus cycles until the correct value is read on
PTJ or PTIJ registers, when changing the DDRJ register.
MC3S12RG128 Data Sheet, Rev. 1.05
104
Freescale Semiconductor