MC3S12RG128 Datasheet, PDF (169/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 5 Interrupt (INTV1) Block Description
5.2 External Signal Description
Most interfacing with the interrupt sub-block is done within the core. However, the interrupt does receive
direct input from the multiplexed external bus interface (MEBI) sub-block of the core for the IRQ and
XIRQ pin data.
5.3 Memory Map and Register Definition
Detailed descriptions of the registers and associated bits are given in the subsections that follow.
5.3.1 Module Memory Map
Name
0x0015
ITCR
0x0016
ITEST
0x001F
HPRIO
Bit 7
R
0
W
R
INTE
W
R
PSEL7
W
6
5
4
3
0
0
WRTINT ADR3
INTC
INTA
INT8
INT6
PSEL6 PSEL5 PSEL4 PSEL3
= Unimplemented or Reserved
Figure 5-2. INT Register Summary
2
ADR2
1
ADR1
INT4
INT2
PSEL2 PSEL1
Bit 0
ADR0
INT0
0
5.3.2 Register Descriptions
5.3.2.1 Interrupt Test Control Register
Module Base + 0x0015
Starting address location affected by INITRG register setting.
7
6
5
4
3
2
R
0
0
0
WRTINT
ADR3
ADR2
W
Reset
0
0
0
0
1
1
= Unimplemented or Reserved
Figure 5-3. Interrupt Test Control Register (ITCR)
Read: See individual bit descriptions
Write: See individual bit descriptions
1
ADR1
1
0
ADR0
1
MC3S12RG128 Data Sheet, Rev. 1.05
Freescale Semiconductor
169