MC3S12RG128 Datasheet, PDF (67/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 1 Device Overview (MC3S12RG128V1)
1.5.1.2 Normal Expanded Narrow Mode
Ports A, B and K are configured as a 23-bit address bus during the address phase, port B is configured as
a 8-bit data bus during the data phase, and port E provides bus control and status signals. This mode allows
8-bit external memory and peripheral devices to be interfaced to the system.
1.5.1.3 Normal Single-Chip Mode
There is no external bus in this mode. The processor program is executed from internal memory. Ports A,
B, K, and most pins of port E are available as general-purpose I/O.
1.5.1.4 Special Single-Chip Mode
This mode is used for debugging single-chip operation, boot-strapping, or security related operations. The
background debug module BDM is active in this mode. The CPU executes a monitor program located in
an on-chip ROM. BDM firmware is waiting for additional serial commands through the BKGD pin. There
is no external bus after reset in this mode.
1.5.1.5 Emulation of Expanded Wide Mode
Developers use this mode for emulation systems in which the users target application is normal expanded
wide mode. Code is executed from external memory or from internal memory depending on the state of
ROMON bit. In this mode the internal operation is visible on external bus interface.
1.5.1.6 Emulation of Expanded Narrow Mode
Developers use this mode for emulation systems in which the users target application is normal expanded
narrow mode. Code is executed from external memory or from internal memory depending on the state of
ROMON bit. In this mode the internal operation is visible on external bus interface.
1.5.1.7 Special Test Mode
Freescale internal use only.
1.5.1.8 Special Peripheral Mode
Freescale internal use only.
1.5.2 Low Power Modes
The microcontroller features three main low power modes. Consult the respective Block User Guide for
information on the module behavior in Stop, Pseudo Stop, and Wait Mode. An important source of
information about the clock system is the Clock and Reset Generator User Guide (CRG).
1.5.2.1 Stop
Executing the CPU STOP instruction stops all clocks and the oscillator thus putting the chip in fully static
mode. Wake up from this mode can be done via reset or external interrupts.
MC3S12RG128 Data Sheet, Rev. 1.05
Freescale Semiconductor
67