MC3S12RG128 Datasheet, PDF (533/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Appendix A Electrical Characteristics
Table A-22. SPI Slave Mode Timing Characteristics
Num
Characteristic
Symbol
Min
1 SCK Frequency
f_sck
DC
1 SCK Period
t_sck
4
2 Enable Lead Time
t_lead
4
3 Enable Lag Time
t_lag
4
4 Clock (SCK) High or Low Time
t_wsck
4
5 Data Setup Time (Inputs)
t_su
8
6 Data Hold Time (Inputs)
t_hi
8
7 Slave Access Time (time to data active)
t_a
—
8 Slave MISO Disable Time
t_dis
—
9 Data Valid after SCK Edge
t_vsck
—
10 Data Valid after SS fall
t_vss
—
11 Data Hold Time (Outputs)
t_ho
20
12 Rise and Fall Time Inputs
t_rfi
—
13 Rise and Fall Time Outputs
t_rfo
—
1 _{tbus added due to internal synchronization delay}
Unit
Typ
Max
—
1/4
f_bus
—
∞
t_bus
—
—
t_bus
—
—
t_bus
—
—
t_bus
—
—
ns
—
—
ns
—
20
ns
—
22
ns
—
30 + t_bus ¹
ns
—
30 + t_bus ¹
ns
—
—
ns
—
8
ns
—
8
ns
A.9 External Bus Timing
A timing diagram of the external multiplexed-bus is illustrated in Figure A-10 with the actual timing
values shown on Table A-23 in 5V range. All major bus signals are included in the diagram. While both a
data write and data read cycle are shown, only one or the other would occur on a particular bus cycle.
A.9.1 General Muxed Bus Timing
The expanded bus timings are highly dependent on the load conditions. The timing parameters shown
assume a balanced load across all outputs.
MC3S12RG128 Data Sheet, Rev. 1.05
Freescale Semiconductor
533