MC3S12RG128 Datasheet, PDF (299/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
Table 10-18. Field Descriptions
Field
Description
7
MCZI
Modulus Counter Underflow Interrupt Enable
0 Modulus counter interrupt is disabled.
1 Modulus counter interrupt is enabled.
6
MODMC
Modulus Mode Enable
0 The counter counts once from the value written to it and will stop at 0x0000.
1 Modulus mode is enabled. When the counter reaches 0x0000, the counter is loaded with the latest value
written to the modulus count register.
Note: For proper operation, the MCEN bit should be cleared before modifying the MODMC bit in order to reset
the modulus counter to 0xFFFF.
5
RDMCL
Read Modulus Down-Counter Load
0 Reads of the modulus count register will return the present value of the count register.
1 Reads of the modulus count register will return the contents of the load register.
4
ICLAT
Input Capture Force Latch Action — When input capture latch mode is enabled (LATQ and BUFEN bit in
ICSYS (0x002B) are set, a write one to this bit immediately forces the contents of the input capture registers TC0
to TC3 and their corresponding 8-bit pulse accumulators to be latched into the associated holding registers. The
pulse accumulators will be automatically cleared when the latch action occurs.
Writing zero to this bit has no effect. Read of this bit will return always zero.
3
FLMC
Force Load Register into the Modulus Counter Count Register — This bit is active only when the modulus
down-counter is enabled (MCEN = 1).
A write one into this bit loads the load register into the modulus counter count register. This also resets the
modulus counter prescaler.
Write zero to this bit has no effect.
When MODMC = 0, counter starts counting and stops at 0x0000.
Read of this bit will return always zero.
2
MCEN
Modulus Down-Counter Enable — When MCEN = 0, the counter is preset to 0xFFFF. This will prevent an early
interrupt flag when the modulus down-counter is enabled.
0 Modulus counter disabled.
1 Modulus counter is enabled.
1–0
Modulus Counter Prescaler Select — These two bits specify the division rate of the modulus counter prescaler.
MCPR[1:0] The newly selected prescaler division rate will not be effective until a load of the load register into the modulus
counter count register occurs. See Table 10-19.
Table 10-19. Modulus Counter Prescaler Select
MCPR1
0
0
1
1
MCPR0
0
1
0
1
Prescaler Division Rate
1
4
8
16
MC3S12RG128 Data Sheet, Rev. 1.05
Freescale Semiconductor
299