MC3S12RG128 Datasheet, PDF (85/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 2 Port Integration Module (PIM3RG128V1) Block Description
2.3.2.2.3 Port S Data Direction Register (DDRS)
Module Base + 0x_000A
R
W
Reset
7
DDRS7
0
6
DDRS6
0
5
DDRS5
0
4
DDRS4
0
3
DDRS3
0
2
DDRS2
0
1
DDRS1
0
0
DDRS0
0
Figure 2-11. Port S Data Direction Register (DDRS)
Read: Anytime.
Write: Anytime.
This register configures each port S pin as either input or output.
• If SPI is enabled, the SPI determines the pin direction. Refer to SPI Block Guide for details.
• If the associated SCI transmit or receive channel is enabled this register has no effect on the pins.
The pin is forced to be an output if a SCI transmit channel is enabled, it is forced to be an input if
the SCI receive channel is enabled.
• The DDRS bits revert to controlling the I/O direction of a pin when the associated channel is
disabled.
Table 2-7. DDRS Field Descriptions
Field
Description
7–0
DDRS[7:0]
Data Direction Port S Bits
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to two bus cycles until the correct value is read on
PTS or PTIS registers, when changing the DDRS register.
MC3S12RG128 Data Sheet, Rev. 1.05
Freescale Semiconductor
85