MC3S12RG128 Datasheet, PDF (232/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 8 Analog-to-Digital Converter (ATD10B8CV3)
Table 8-19. Special Channel Select Coding
SC
CC
CB
1
0
X
1
1
0
1
1
0
1
1
1
1
1
1
CA
Analog Input Channel
X
Reserved
0
V_RH
1
V_RL
0
(V_RH+V_RL) / 2
1
Reserved
8.3.2.10 ATD Status Register 1 (ATDSTAT1)
This read-only register contains the conversion complete flags.
Module Base + 0x000B
R
W
Reset
7
CCF7
0
6
CCF6
5
CCF5
4
CCF4
3
CCF3
2
CCF2
0
0
0
0
0
= Unimplemented or Reserved
Figure 8-12. ATD Status Register 1 (ATDSTAT1)
Read: Anytime
Write: Anytime, no effect
Table 8-20. ATDSTAT1 Field Descriptions
1
CCF1
0
0
CCF0
0
Field
7–0
CCF[7:0]
Description
Conversion Complete Flag x (x = 7, 6, 5, 4, 3, 2, 1, 0) — A conversion complete flag is set at the end of each
conversion in a conversion sequence. The flags are associated with the conversion position in a sequence (and
also the result register number). Therefore, CCF0 is set when the first conversion in a sequence is complete and
the result is available in result register ATDDR0; CCF1 is set when the second conversion in a sequence is
complete and the result is available in ATDDR1, and so forth. A flag CCFx (x = 7, 6, 5, 4, 3, 2,1, 70) is cleared
when ADPU=1 and one of the following occurs:
A) Write to ATDCTL5 (a new conversion sequence is started)
B) If AFFC=0 and read of ATDSTAT1 followed by read of result register ATDDRx
C) If AFFC=1 and read of result register ATDDRx
In case of a concurrent set and clear on CCFx: The clearing by method A) will overwrite the set. The clearing by
methods B) or C) will be overwritten by the set.
0 Conversion number x not completed
1 Conversion number x has completed, result ready in ATDDRx
MC3S12RG128 Data Sheet, Rev. 1.05
232
Freescale Semiconductor