MC3S12RG128 Datasheet, PDF (131/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 4
Multiplexed External Bus Interface (MEBIV3)
Block Description
4.1 Introduction
This section describes the functionality of the multiplexed external bus interface (MEBI) sub-block of the
S12 core platform. The functionality of the module is closely coupled with the S12 CPU and the memory
map controller (MMC) sub-blocks.
Figure 4-1 is a block diagram of the MEBI. In Figure 4-1, the signals on the right hand side represent pins
that are accessible externally. On some chips, these may not all be bonded out.
The MEBI sub-block of the core serves to provide access and/or visibility to internal core data
manipulation operations including timing reference information at the external boundary of the core and/or
system. Depending upon the system operating mode and the state of bits within the control registers of the
MEBI, the internal 16-bit read and write data operations will be represented in 8-bit or 16-bit accesses
externally. Using control information from other blocks within the system, the MEBI will determine the
appropriate type of data access to be generated.
4.1.1 Features
The block name includes these distinctive features:
• External bus controller with four 8-bit ports A,B, E, and K
• Data and data direction registers for ports A, B, E, and K when used as general-purpose I/O
• Control register to enable/disable alternate functions on ports E and K
• Mode control register
• Control register to enable/disable pull-ups on ports A, B, E, and K
• Control register to enable/disable reduced output drive on ports A, B, E, and K
• Control register to configure external clock behavior
• Control register to configure IRQ pin operation
• Logic to capture and synchronize external interrupt pin inputs
MC3S12RG128 Data Sheet, Rev. 1.05
Freescale Semiconductor
131