MC3S12RG128 Datasheet, PDF (51/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 1 Device Overview (MC3S12RG128V1)
Table 1-4. Signal Properties Summary (Sheet 1 of 3)
Pin
Name
Function 1
Pin
Name
Function 2
Pin
Name
Function 3
Pin
Name
Function 4
Pin
Name
Function 5
Power
Supply
Internal Pull
Resistor
CTRL
Reset
State
Description
EXTAL
—
—
—
XTAL
—
—
—
RESET
—
—
—
TEST
—
—
—
VREGEN
—
—
—
XFC
—
—
—
BKGD
TAGHI
MODC
—
PAD[15] AN1[7] ETRIG1
—
PAD[14:8] AN1[6:0]
—
—
PAD[7]
AN0[7] ETRIG0
—
PAD[6:0] AN0[6:0]
—
—
PA[7:0] ADDR[15:8] —
—
/
DATA[15:8]
PB[7:0] ADDR[7:0]/
—
—
DATA[7:0]
PE7
NOACC XCLKS
—
PE6
IPIPE1
MODB
—
PE5
IPIPE0
MODA
—
PE4
ECLK
—
—
PE3
LSTRB TAGLO
—
PE2
R/W
—
—
PE1
IRQ
—
—
PE0
XIRQ
—
—
—
V_DDPLL
NA
—
V_DDPLL
NA
—
V_DDR
None
—
V_DDR
None
—
V_DDX
NA
NA
NA
None
None
NA
Oscillator Pins
External Reset
Test Input
Voltage Regulator Enable
Input
—
V_DDPLL
NA
NA PLL Loop Filter
—
V_DDR Always Up
Up Background Debug, Tag
High, Mode Input
—
V_DDA
None
None Port AD Input, Analog
Inputs, External Trigger
Input (ATD1)
—
V_DDA
None
None Port AD Input, Analog
Inputs (ATD1)
—
V_DDA
None
None Port AD Input, Analog
Inputs, External Trigger
Input (ATD0)
—
V_DDA
None
None Port AD Input, Analog Inputs
(ATD0)
—
V_DDR
PUCR/ Disabled Port A I/O, Multiplexed
PUPAE
Address/Data
—
V_DDR
PUCR/ Disabled Port B I/O, Multiplexed
PUPBE
Address/Data
—
V_DDR
PUCR/
Mode Port E I/O, Access, Clock
PUPEE depen- Select
dant¹
—
V_DDR While RESET pin low: Port E I/O, Pipe Status,
Down
Mode Input
—
V_DDR
Port E I/O, Pipe Status,
Mode Input
—
V_DDR
PUCR/
Mode Port E I/O, Bus Clock Output
PUPEE depen-
—
V_DDR
PUCR/
dant¹ _{Port E I/O, Byte Strobe, Tag}
PUPEE
Low
—
V_DDR
PUCR/
PUPEE
Port E I/O, R/W in expanded
modes
—
V_DDR
PUCR/
Up Port E Input, Maskable
PUPEE
Interrupt
—
V_DDR
PUCR/
PUPEE
Port E Input, Non Maskable
Interrupt
MC3S12RG128 Data Sheet, Rev. 1.05
Freescale Semiconductor
51