MC3S12RG128 Datasheet, PDF (303/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
10.3.2.23 Input Control Overwrite Register (ICOVW)
Module Base + 0x002A
R
W
Reset
7
NOVW7
0
6
NOVW6
5
NOVW5
4
NOVW4
3
NOVW3
2
NOVW2
1
NOVW1
0
0
0
0
0
0
Figure 10-27. Input Control Overwrite Register (ICOVW))
0
NOVW0
0
Read or write anytime.
An IC register is empty when it has been read or latched into the holding register.
A holding register is empty when it has been read.
Table 10-24. ICOVW Field Descriptions
Field
Description
7–0
NOVW[7:0]
No Input Capture Overwrite
0 The contents of the related capture register or holding register can be overwritten when a new input capture
or latch occurs.
1 The related capture register or holding register cannot be written by an event unless they are empty (see
Section 10.4.1.1, “IC Channels”). This will prevent the captured value to be overwritten until it is read or
latched in the holding register.
10.3.2.24 Input Control System Control Register (ICSYS)
Module Base + 0x002B
R
W
Reset
7
SH37
0
6
SH26
5
SH15
4
SH04
3
TFMOD
2
PACMX
0
0
0
0
0
Figure 10-28. Input Control System Register (ICSYS)
1
BUFEN
0
0
LATQ
0
Read: Anytime
Write: Can be written once (test_mode = 0). Writes are always permitted when test_mode = 1.
Table 10-25. ICSYS Field Descriptions
Field
Description
7–4
Share Input action of Input Capture Channels x and y
SH37, SH26, 0 Normal operation
SH15, SH04 1 The channel input ‘x’ causes the same action on the channel ‘y’. The port pin ‘x’ and the corresponding edge
detector is used to be active on the channel ‘y’.
MC3S12RG128 Data Sheet, Rev. 1.05
Freescale Semiconductor
303