MC3S12RG128 Datasheet, PDF (315/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
If the corresponding NOVWn bit of the ICOVW register is set, the capture register or its
holding register cannot be written by an event unless they are empty (see Section 10.4.1.1, “IC
Channels”). This will prevent the captured value to be overwritten until it is read or latched in
the holding register.
2. IC queue mode:
When enabled (LATQ = 0), the main timer value is memorized in the IC register by a valid
input pin transition. See Figure 10-38.
If the corresponding NOVWn bit of the ICOVW register is cleared, with a new occurrence of
a capture, the value of the IC register will be transferred to its holding register and the IC
register memorizes the new timer value.
If the corresponding NOVWn bit of the ICOVW register is set, the capture register or its
holding register cannot be written by an event unless they are empty (see Section 10.4.1.1, “IC
Channels”).
In queue mode, reads of holding register will latch the corresponding pulse accumulator value
to its holding register.
10.4.1.1.3 Delayed IC Channels
There are four delay counters in this module associated with IC channels 0–3. The use of this feature is
explained in the diagram (Figure 10-42) and notes below.
BUS CLOCK
DLY_CNT
0
1
2
3
253 ₂₅₄ 255 256
INPUT ON
CH0–CH3
INPUT ON
CH0–CH3
INPUT ON
CH0–CH3
255 CYCLES
255.5 CYCLES
255.5 CYCLES
REJECTED
REJECTED
ACCEPTED
INPUT ON
CH0–CH3
256 CYCLES
ACCEPTED
Figure 10-42. Channel Input Validity with Delay Counter Feature
In the diagram shown in Figure 10-42 a delay counter value of 256 bus cycles is considered.
1. Input pulses with a duration of (DLY_CNT – 1) cycles or shorter are rejected.
2. Input pulses with a duration between (DLY_CNT – 1) and DLY_CNT cycles may be rejected or
accepted, depending on their relative alignment with the sample points.
MC3S12RG128 Data Sheet, Rev. 1.05
Freescale Semiconductor
315