MC3S12RG128 Datasheet, PDF (531/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Appendix A Electrical Characteristics
SS¹
(OUTPUT)
SCK
(CPOL = 0)
(OUTPUT)
SCK
(CPOL = 1)
(OUTPUT)
MISO
(INPUT)
1
2
4
4
5
6
MSB IN²
9
MOSI
(OUTPUT)
PORT DATA
MASTER MSB OUT²
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
12
12
BIT 6 . . . 1
11
BIT 6 . . . 1
13
3
13
LSB IN
MASTER LSB OUT
Figure A-7. SPI Master Timing (CPHA=1)
In Table A-21 the timing characteristics for master mode are listed.
Table A-21. SPI Master Mode Timing Characteristics
PORT DATA
Num
Characteristic
1 SCK Frequency
1 SCK Period
2 Enable Lead Time
3 Enable Lag Time
4 Clock (SCK) High or Low Time
5 Data Setup Time (Inputs)
6 Data Hold Time (Inputs)
9 Data Valid after SCK Edge
10 Data Valid after SS fall (CPHA=0)
11 Data Hold Time (Outputs)
12 Rise and Fall Time Inputs
13 Rise and Fall Time Outputs
Symbol
Min
Typ
f_sck
1/2048
—
t_sck
2
—
t_lead
—
1/2
t_lag
—
1/2
t_wsck
—
1/2
t_su
8
—
t_hi
8
—
t_vsck
—
—
t_vss
—
—
t_ho
20
—
t_rfi
—
—
t_rfo
—
—
Max
1/2
2048
—
—
—
—
—
30
15
—
8
8
Unit
f_bus
t_bus
t_sck
t_sck
t_sck
ns
ns
ns
ns
ns
ns
ns
A.8.2 Slave Mode
In Figure A-8 the timing diagram for slave mode with transmission format CPHA=0 is depicted.
MC3S12RG128 Data Sheet, Rev. 1.05
Freescale Semiconductor
531