MC3S12RG128 Datasheet, PDF (284/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
10.3.2.2 Timer Compare Force Register (CFORC)
Module Base + 0x0001
R
W
Reset
7
0
FOC7
0
6
5
4
3
2
0
0
0
0
0
FOC6
FOC5
FOC4
FOC3
FOC2
0
0
0
0
0
Figure 10-4. Timer Compare Force Register (CFORC)
Read anytime but will always return 0x0000 (1 state is transient). Write anytime.
Table 10-2. CFORC Field Descriptions
1
0
FOC1
0
0
0
FOC0
0
Field
Description
7–0
FOC[7:0]
Force Output Compare Action for Channel 7–0 — A write to this register with the corresponding data bit(s)
set causes the action which is programmed for output compare “n” to occur immediately. The action taken is the
same as if a successful comparison had just taken place with the TCn register except the interrupt flag does not
get set.
Note: A successful channel 7 output compare overrides any channel 6:0 compares.If forced output compare on
any channel occurs at the same time as the successful output compare then forced output compare action
will take precedence and interrupt flag won’t get set.
10.3.2.3 Output Compare 7 Mask Register (OC7M)
Module Base + 0x0002
R
W
Reset
7
OC7M7
0
6
OC7M6
5
OC7M5
4
OC7M4
3
OC7M3
2
OC7M2
0
0
0
0
0
Figure 10-5. Output Compare 7 Mask Register (OC7M)
1
OC7M1
0
0
OC7M0
0
Read or write anytime.
Setting the OC7Mn (n ranges from 0 to 6) bit of OC7M register configures the corresponding port to be
an output port when the IOS7 bit and the corresponding IOSn (n ranges from 0 to 6) bit of TIOS register
are set to be an output compare. Refer to the note on Section 10.4.1.4, “Channel Configurations” for more
insight.
NOTE
A successful channel 7 output compare overrides any channel 6:0 compares.
For each OC7M bit that is set, the output compare action reflects the
corresponding OC7D bit.
MC3S12RG128 Data Sheet, Rev. 1.05
284
Freescale Semiconductor