MC3S12RG128 Datasheet, PDF (110/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 2 Port Integration Module (PIM3RG128V1) Block Description
Table 2-42. Implemented Modules on Derivatives
Number
of Modules
2
1
MSCAN Modules
CAN0
X
X
CAN4
X
—
SPI Modules
SPI0
X
X
SPI1
X
—
2.4.10 Port P
This port is associated with the PWM and SPI1.
Port P pins PP[7:0] can be used for either general purpose I/O, or with the PWM and SPI subsystems.
The pins are shared between the PWM channels and the SPI1 module. If the PWM is enabled the pins
become PWM output channels with the exception of pin 7 which can be PWM input or output. If SPI1 is
enabled and PWM is disabled, the respective pin configuration is determined by several status bits in the
SPI1 module. During reset, port P pins are configured as high-impedance inputs.
The SPI1 pins can be re-routed. Refer to Figure 2-23.
Port P offers eight I/O pins with edge triggered interrupt capability in wired-OR fashion. The interrupt
enable as well as the sensitivity to rising or falling edges can be individually configured on per pin basis.
All eight bits/pins share the same interrupt vector. Interrupts can be used with the pins configured as inputs
or outputs.
An interrupt is generated when a bit in the port interrupt flag register and its corresponding port interrupt
enable bit are both set. This external interrupt feature is capable to wake up the CPU when it is in Stop or
Wait mode.
A digital filter on each pin prevents pulses (Figure 2-50) shorter than a specified time from generating an
interrupt. The minimum time varies over process conditions, temperature and voltage (Figure 2-49 and
Table 2-43).
GLITCH, FILTERED OUT, NO INTERRUPT FLAG SET
VALID PULSE, INTERRUPT FLAG SET
UNCERTAIN
t_pign
t_pval
Figure 2-49. Interrupt Glitch Filter on Port P, H, and J (PPS = 0)
MC3S12RG128 Data Sheet, Rev. 1.05
110
Freescale Semiconductor