MC3S12RG128 Datasheet, PDF (308/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
10.3.2.28 Modulus Down-Counter Count Register (MCCNT)
Module Base + 0x0036–0x0037
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R mccnt mccnt mccnt mccnt mccnt mccnt mccnt mccnt mccnt mccnt mccnt mccnt mccnt mccnt mccnt mccnt
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Figure 10-32. Modulus Down-Counter Count Register (MCCNT)
Read or write anytime.
A full access for the counter register should take place in one clock cycle. A separate read/write for high
byte and low byte will give different result than accessing them as a word.
If the RDMCL bit in MCCTL register is cleared, reads of the MCCNT register will return the present value
of the count register. If the RDMCL bit is set, reads of the MCCNT will return the contents of the load
register.
If a 0x0000 is written into MCCNT and modulus counter while LATQ and BUFEN in ICSYS (0x002B)
register are set, the input capture and pulse accumulator registers will be latched.
With a 0x0000 write to the MCCNT, the modulus counter will stay at zero and does not set the MCZF flag
in MCFLG register.
If modulus mode is enabled (MODMC = 1), a write to this address will update the load register with the
value written to it. The count register will not be updated with the new value until the next counter
underflow.
The FLMC bit in MCCTL (0x0026) can be used to immediately update the count register with the new
value if an immediate load is desired.
If modulus mode is not enabled (MODMC = 0), a write to this address will clear the prescaler and will
immediately update the counter register with the value written to it and down-counts once to 0x0000.
MC3S12RG128 Data Sheet, Rev. 1.05
308
Freescale Semiconductor