MC3S12RG128 Datasheet, PDF (239/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 8 Analog-to-Digital Converter (ATD10B8CV3)
8.5.1.5 Step 5
Configure starting channel, single/multiple channel, continuous or single sequence and result data format
in ATDCTL5. Writing ATDCTL5 will start the conversion, so make sure your write ATDCTL5 in the last
step.
Example: Leave CC,CB,CA clear to start on channel AN0. Write MULT=1 to convert channel AN0 to
AN3 in a sequence (4 conversion per sequence selected in ATDCTL3).
8.5.2 Aborting an A/D conversion
8.5.2.1 Step 1
Write to ATDCTL4. This will abort any ongoing conversion sequence.
(Do not use write to other ATDCTL registers to abort, as this under certain circumstances might not work
correctly.)
8.5.2.2 Step 2
Disable the ATD Interrupt by writing ASCIE=0 in ATDCTL2.
It is important to clear the interrupt enable at this point, prior to step 3, as depending on the device clock
gating it may not always be possible to clear it or the SCF flag once the module is disabled (ADPU=0).
8.5.2.3 Step 3
Clear the SCF flag by writing a 1 in ATDSTAT0.
(Remaining flags will be cleared with the next start of a conversions, but SCF flag should be cleared to
avoid SCF interrupt.)
8.5.2.4 Step 4
Power down ATD by writing ADPU=0 in ATDCTL2.
8.6 Resets
At reset the ATD is in a power down state. The reset state of each individual bit is listed within the Register
Description section (see Section 8.3, “Memory Map and Register Definition”), which details the registers
and their bit-field.
8.7 Interrupts
The interrupt requested by the ATD is listed in Table 8-24. Refer to the device overview chapter for related
vector address and priority.
MC3S12RG128 Data Sheet, Rev. 1.05
Freescale Semiconductor
239