MC3S12RG128 Datasheet, PDF (302/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
10.3.2.22 Delay Counter Control Register (DLYCT)
Module Base + 0x0029
7
6
5
4
3
2
1
R
0
0
0
0
0
0
DLY1
W
Reset
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 10-26. Delay Counter Control Register (DLYCT)
0
DLY0
0
Read or write anytime.
If enabled, after detection of a valid edge on input capture pin, the delay counter counts the pre-selected
number of bus clock cycles, then it will generate a pulse on its output. The pulse is generated only if the
level of input signal, after the preset delay, is the opposite of the level before the transition.This will avoid
reaction to narrow input pulses.
After counting, the counter will be cleared automatically.
Delay between two active edges of the input signal period should be longer than the selected counter delay.
Table 10-22. DLYCT Field Descriptions
Field
1–0
DLY[1:0]
Delay Counter Select — See Table 10-23.
Description
DLY1
0
0
1
1
Table 10-23. Delay Counter Select
DLY0
0
1
0
1
Delay
Disabled (bypassed)
256 bus clock cycles
512 bus clock cycles
1024 bus clock cycles
MC3S12RG128 Data Sheet, Rev. 1.05
302
Freescale Semiconductor