MC3S12RG128 Datasheet, PDF (376/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 12 Freescale’s Scalable Controller Area Network (MSCANV2)
Module Base + 0x00X3
7
6
5
4
3
2
1
0
R
W
Reset:
x
x
x
x
x
x
x
x
= Unused; always read ‘x’
Figure 12-32. Identifier Register 3 — Standard Mapping
12.3.3.2 Data Segment Registers (DSR0-7)
The eight data segment registers, each with bits DB[7:0], contain the data to be transmitted or received.
The number of bytes to be transmitted or received is determined by the data length code in the
corresponding DLR register.
Module Base + 0x0004 (DSR0)
0x0005 (DSR1)
0x0006 (DSR2)
0x0007 (DSR3)
0x0008 (DSR4)
0x0009 (DSR5)
0x000A (DSR6)
0x000B (DSR7)
7
R
DB7
W
6
DB6
5
DB5
4
DB4
3
DB3
2
DB2
1
DB1
0
DB0
Reset:
x
x
x
x
x
x
x
x
Figure 12-33. Data Segment Registers (DSR0–DSR7) — Extended Identifier Mapping
Field
7:0
DB[7:0]
Table 12-30. DSR0–DSR7 Register Field Descriptions
Data bits 7:0
Description
MC3S12RG128 Data Sheet, Rev. 1.05
376
Freescale Semiconductor