MC3S12RG128 Datasheet, PDF (364/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 12 Freescale’s Scalable Controller Area Network (MSCANV2)
The IDHITx indicators are always related to the message in the foreground buffer (RxFG). When a
message gets shifted into the foreground buffer of the receiver FIFO the indicators are updated as well.
12.3.2.13 MSCAN Reserved Registers
These registers are reserved for factory testing of the MSCAN module and is not available in normal
system operation modes.
Module Base + 0x000C, 0x000D
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 12-16. MSCAN Reserved Registers
Read: Always read 0x0000 in normal system operation modes
Write: Unimplemented in normal system operation modes
NOTE
Writing to this register when in special modes can alter the MSCAN
functionality.
12.3.2.14 MSCAN Receive Error Counter (CANRXERR)
This register reflects the status of the MSCAN receive error counter.
Module Base + 0x000E
7
R RXERR7
6
RXERR6
5
RXERR5
4
RXERR4
3
RXERR3
2
RXERR2
1
RXERR1
W
Reset:
0
0
0
0
0
0
0
= Unimplemented
Figure 12-17. MSCAN Receive Error Counter (CANRXERR)
0
RXERR0
0
Read: Only when in sleep mode (SLPRQ = 1 and SLPAK = 1) or initialization mode (INITRQ = 1 and
INITAK = 1)
Write: Unimplemented
MC3S12RG128 Data Sheet, Rev. 1.05
364
Freescale Semiconductor