MC3S12RG128 Datasheet, PDF (97/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 2 Port Integration Module (PIM3RG128V1) Block Description
2.3.2.5.6 Port P Polarity Select Register (PPSP)
Module Base + 0x_001D
R
W
Reset
7
PPSP7
0
Read: Anytime.
6
PPSP6
5
PPSP5
4
PPSP4
3
PPSP3
2
PPSP2
0
0
0
0
0
Figure 2-29. Port P Polarity Select Register (PPSP)
1
PPSP1
0
0
PPSP0
0
Write: Anytime.
This register serves a dual purpose by selecting the polarity of the active interrupt edge as well as selecting
a pull-up or pull-down device if enabled.
Table 2-26. PPSP Field Descriptions
Field
Description
7–0
PPSP[7:0]
Polarity Select Port P Bits
0 Falling edge on the associated port P pin sets the associated flag bit in the PIFP register. A pull-up device is
connected to the associated port P pin, if enabled by the associated bit in register PERP and if the port is used
as input.
1 Rising edge on the associated port P pin sets the associated flag bit in the PIFP register. A pull-down device
is connected to the associated port P pin, if enabled by the associated bit in register PERP and if the port is
used as input.
2.3.2.5.7 Port P Interrupt Enable Register (PIEP)
Module Base + 0x_001E
7
R
PIEP7
W
6
PIEP6
5
PIEP5
4
PIEP4
3
PIEP3
2
PIEP2
1
PIEP1
0
PIEP0
Reset
0
0
0
0
0
0
0
0
Read: Anytime.
Figure 2-30. Port P Interrupt Enable Register (PIEP)
Write: Anytime.
This register disables or enables on a per pin basis the edge sensitive external interrupt associated with
port P.
Table 2-27. PIEP Field Descriptions
Field
Description
7–0
PIEP[7:0]
Interrupt Enable Port P Bits
0 Interrupt is disabled (interrupt flag masked).
1 Interrupt is enabled.
MC3S12RG128 Data Sheet, Rev. 1.05
Freescale Semiconductor
97