MC3S12RG128 Datasheet, PDF (64/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 1 Device Overview (MC3S12RG128V1)
Consult the CRG Block User Guide for details on clock generation.
EXTAL
XTAL
CRG
bus clock
oscillator clock
core clock
HCS12 CORE
BDM CPU
MEBI MMC
INT BKP
ROM
RAM
ECT
ATD0, ATD1
PWM
SCI0, SCI1
SPI0, SPI1
CAN0, CAN4
IIC
PIM
Figure 1-10. Clock Connections
1.4 Chip Configuration Summary
Eight possible modes determine the operating configuration of the MC3S12RG128. Each mode has an
associated default memory map and external bus configuration controlled by a further pin.
Three low power modes exist for the device.
The operating mode out of reset is determined by the states of the MODC, MODB, and MODA pins during
reset (Table 1-6). The MODC, MODB, and MODA bits in the MODE register show the current operating
mode and provide limited mode switching during operation. The states of the MODC, MODB, and MODA
pins are latched into these bits on the rising edge of the reset signal. The ROMCTL signal allows the setting
of the ROMON bit in the MISC register thus controlling whether the internal ROM is visible in the
memory map. ROMON = 1 mean the ROM is visible in the memory map. The state of the ROMCTL pin
is latched into the ROMON bit in the MISC register on the rising edge of the reset signal.
MC3S12RG128 Data Sheet, Rev. 1.05
64
Freescale Semiconductor