MC3S12RG128 Datasheet, PDF (280/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
10.3 Memory Map and Registers
This section provides a detailed description of all memory and registers.
10.3.1 Module Memory Map
A register summary for the ECT module is given below in Figure 10-2. The Address listed for each register
is the address offset. The total address for each register is the sum of the base address for the ECT module
and the address offset for each register.
Address
0x0000
0x0001
0x0002
0x0003
0x0004
0x0005
0x0006
0x0007
0x0008
0x0009
0x000A
0x000B
0x000C
0x000D
0x000E
0x000F
0x0010
Name
TIOS
CFORC
OC7M
OC7D
TCNT
TCNT
TSCR1
TTOV
TCTL1
TCTL2
TCTL3
TCTL4
TIE
TSCR2
TFLG1
TFLG2
TC0
Bit 7
R
IOS7
W
R0
W FOC7
R
OC7M7
W
R
OC7D7
W
R
TCNT15
W
R
TCNT7
W
R
TEN
W
R
TOV7
W
R
OM7
W
R
OM3
W
R
EDG7B
W
R
EDG3B
W
R
C7I
W
R
TOI
W
R
C7F
W
R
TOF
W
R
TC015
W
6
IOS6
0
FOC6
OC7M6
OC7D6
TCNT14
TCNT6
TSWAI
TOV6
OL7
OL3
EDG7A
EDG3A
C6I
0
C6F
0
TC014
5
IOS5
0
FOC5
OC7M5
OC7D5
TCNT13
TCNT5
TSFRZ
TOV5
OM6
OM2
EDG6B
EDG2B
C5I
0
C5F
0
TC013
4
IOS4
0
FOC4
OC7M4
OC7D4
TCNT12
TCNT4
TFFCA
TOV4
OL6
OL2
EDG6A
EDG2A
C4I
0
C4F
0
TC012
3
IOS3
0
FOC3
OC7M3
OC7D3
TCNT11
TCNT3
0
TOV3
OM5
OM1
EDG5B
EDG1B
C3I
TCRE
C3F
0
TC011
2
IOS2
0
FOC2
OC7M2
OC7D2
TCNT10
TCNT2
0
TOV2
OL5
OL1
EDG5A
EDG1A
C2I
PR2
C2F
0
TC010
1
IOS1
0
FOC1
OC7M1
OC7D1
TCNT9
TCNT1
0
TOV1
OM4
OM0
EDG4B
EDG0B
C1I
PR1
C1F
0
TC09
Bit 0
IOS0
0
FOC0
OC7M0
OC7D0
TCNT8
TCNT0
0
TOV0
OL4
OL0
EDG4A
EDG0A
C0I
PR0
C0F
0
TC08
= Unimplemented or Reserved
Figure 10-2. ECT Register Summary (Sheet 1 of 4)
MC3S12RG128 Data Sheet, Rev. 1.05
280
Freescale Semiconductor