MC3S12RG128 Datasheet, PDF (365/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 12 Freescale’s Scalable Controller Area Network (MSCANV2)
NOTE
Reading this register when in any other mode other than sleep or
initialization mode may return an incorrect value. For MCUs with dual
CPUs, this may result in a CPU fault condition.
Writing to this register when in special modes can alter the MSCAN
functionality.
12.3.2.15 MSCAN Transmit Error Counter (CANTXERR)
This register reflects the status of the MSCAN transmit error counter.
Module Base + 0x000F
7
R TXERR7
6
TXERR6
5
TXERR5
4
TXERR4
3
TXERR3
2
TXERR2
1
TXERR1
W
Reset:
0
0
0
0
0
0
0
= Unimplemented
Figure 12-18. MSCAN Transmit Error Counter (CANTXERR)
0
TXERR0
0
Read: Only when in sleep mode (SLPRQ = 1 and SLPAK = 1) or initialization mode (INITRQ = 1 and
INITAK = 1)
Write: Unimplemented
NOTE
Reading this register when in any other mode other than sleep or
initialization mode, may return an incorrect value. For MCUs with dual
CPUs, this may result in a CPU fault condition.
Writing to this register when in special modes can alter the MSCAN
functionality.
MC3S12RG128 Data Sheet, Rev. 1.05
Freescale Semiconductor
365