MC3S12RG128 Datasheet, PDF (297/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
10.3.2.17 Pulse Accumulators Count Registers (PACN3/PACN2)
Module Base + 0x0022
7
6
5
4
3
2
1
R
PACNT7(15) PACNT6(14) PACNT5(13) PACNT4(12) PACNT3(11) PACNT2(10) PACNT1(9)
W
0
PACNT0(8)
Reset
0
0
0
0
0
0
0
0
Figure 10-19. Pulse Accumulators Count Register 3 (PACN3)
Module Base + 0x0023
R
W
Reset
7
PACNT7
0
6
PACNT6
5
PACNT5
4
PACNT4
3
PACNT3
2
PACNT2
1
PACNT1
0
0
0
0
0
0
Figure 10-20. Pulse Accumulators Count Register 2 (PACN2)
0
PACNT0
0
Read or write anytime.
The two 8-bit pulse accumulators PAC3 and PAC2 are cascaded to form the PACA 16-bit pulse
accumulator. When PACA in enabled (PAEN = 1 in PACTL, 0x0020) the PACN3 and PACN2 registers
contents are respectively the high and low byte of the PACA.
When PACN3 overflows from 0x00FF to 0x0000, the Interrupt flag PAOVF in PAFLG (0x0021) is set.
Full count register access should take place in one clock cycle. A separate read/write for high byte and low
byte will give a different result than accessing them as a word.
NOTE
When clocking pulse and write to the registers occurs simultaneously, write
takes priority and the register is not incremented.
MC3S12RG128 Data Sheet, Rev. 1.05
Freescale Semiconductor
297