MC3S12RG128 Datasheet, PDF (87/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 2 Port Integration Module (PIM3RG128V1) Block Description
2.3.2.2.6 Port S Polarity Select Register (PPSS)
Module Base + 0x_000D
R
W
Reset
7
PPSS7
0
6
PPSS6
5
PPSS5
4
PPSS4
3
PPSS3
2
PPSS2
0
0
0
0
0
Figure 2-14. Port S Polarity Select Register (PPSS)
1
PPSS1
0
Read: Anytime.
Write: Anytime.
This register selects whether a pull-down or a pull-up device is connected to the pin.
Table 2-10. PPSS Field Descriptions
0
PPSS0
0
Field
Description
7–0
PPSS[7:0]
Pull Select Port S Bits
0 A pull-up device is connected to the associated port S pin, if enabled by the associated bit in register PERS
and if the port is used as input or as wired-OR output.
1 A pull-down device is connected to the associated port S pin, if enabled by the associated bit in register PERS
and if the port is used as input.
2.3.2.2.7 Port S Wire-OR Mode Register (WOMS)
Module Base + 0x_000E
R
W
Reset
7
WOMS7
0
6
WOMS6
5
WOMS5
4
WOMS4
3
WOMS3
2
WOMS2
0
0
0
0
0
Figure 2-15. Port S Wired-OR Mode Register (WOMS)
1
WOMS1
0
0
WOMS0
0
Read: Anytime.
Write: Anytime.
This register configures the output pins as wired-OR. If enabled the output is driven active low only
(open-drain). A logic level of “1” is not driven. It applies also to the SPI and SCI outputs and allows a
multipoint connection of several serial modules. This bit has no influence on pins used as inputs.
Table 2-11. WOMS Field Descriptions
Field
Description
7–0
Wired-OR Mode Port S Bits
WOMS[7:0] 0 Output buffers operate as push-pull outputs.
1 Output buffers operate as open-drain outputs.
MC3S12RG128 Data Sheet, Rev. 1.05
Freescale Semiconductor
87