MC3S12RG128 Datasheet, PDF (295/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
Table 10-14. PACTL Field Descriptions (continued)
Field
4
PEDGE
3–2
CLK[1:0]
1
PAOVI
Description
Pulse Accumulator Edge Control — This bit is active only when the Pulse Accumulator A is enabled
(PAEN = 1). See Table 10-15.
For PAMOD bit = 0 (event counter mode).
0 Falling edges on PT7 pin cause the count to be incremented
1 Rising edges on PT7 pin cause the count to be incremented
For PAMOD bit = 1 (gated time accumulation mode).
0 PT7 input pin high enables bus clock divided by 64 to Pulse Accumulator and the trailing falling edge on PT7
sets the PAIF flag.
1 PT7 input pin low enables bus clock divided by 64 to Pulse Accumulator and the trailing rising edge on PT7
sets the PAIF flag
Note: If the timer is not active (TEN = 0 in TSCR), there is no divide-by-64 since the ÷64 clock is generated by
the timer prescaler.
Clock Select Bits — If the pulse accumulator is disabled (PAEN = 0), the prescaler clock from the timer is always
used as an input clock to the timer counter. The change from one selected clock to the other happens
immediately after these bits are written.
Refer to Table 10-16 and for the description of PACLK please refer Figure 10-17.
Pulse Accumulator A Overflow Interrupt Enable
0 Interrupt inhibited
1nterrupt requested if PAOVF is set
0
Pulse Accumulator Input Interrupt Enable
PAI
0 Interrupt inhibited
1 Interrupt requested if PAIF is set
PAMOD
0
0
1
1
PEDGE
0
1
0
1
Table 10-15. Pin Action
Pin Action
Falling edge
Rising edge
Divide by 64 clock enabled with pin high level
Divide by 64 clock enabled with pin low level
CLK1
0
0
1
1
CLK0
0
1
0
1
Table 10-16. Clock Selection
Clock Source
Use timer prescaler clock as timer counter clock
Use PACLK as input to timer counter clock
Use PACLK/256 as timer counter clock frequency
Use PACLK/65536 as timer counter clock frequency
MC3S12RG128 Data Sheet, Rev. 1.05
Freescale Semiconductor
295