MC3S12RG128 Datasheet, PDF (344/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 12 Freescale’s Scalable Controller Area Network (MSCANV2)
12.1.2 Block Diagram
Oscillator Clock
Bus Clock
MSCAN
CANCLK
Tq Clk
MUX
Presc.
Receive/
Transmit
Engine
RXCAN
TXCAN
Transmit Interrupt Req.
Receive Interrupt Req.
Errors Interrupt Req.
Wake-Up Interrupt Req.
Control
and
Status
Configuration
Registers
Message
Filtering
and
Buffering
Wake-Up
Low Pass Filter
Figure 12-1. MSCAN Block Diagram
12.1.3 Features
The basic features of the MSCAN are as follows:
• Implementation of the CAN protocol — Version 2.0A/B
— Standard and extended data frames
— Zero to eight bytes data length
— Programmable bit rate up to 1 Mbps¹
— Support for remote frames
• Five receive buffers with FIFO storage scheme
• Three transmit buffers with internal prioritization using a “local priority” concept
• Flexible maskable identifier filter supports two full-size (32-bit) extended identifier filters, or four
16-bit filters, or eight 8-bit filters
• Programmable wakeup functionality with integrated low-pass filter
• Programmable loopback mode supports self-test operation
• Programmable listen-only mode for monitoring of CAN bus
• Separate signalling and interrupt capabilities for all CAN receiver and transmitter error states
(warning, error passive, bus-off)
• Programmable MSCAN clock source either bus clock or oscillator clock
• Internal timer for time-stamping of received and transmitted messages
• Three low-power modes: sleep, power down, and MSCAN enable
1. Depending on the actual bit timing and the clock jitter of the PLL.
MC3S12RG128 Data Sheet, Rev. 1.05
344
Freescale Semiconductor