MC3S12RG128 Datasheet, PDF (325/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

SCL
SDA
Chapter 11 Inter-Integrated Circuit (IICV2) Block Description
SCL Divider
SDA Hold
SDA
SCL
SCL Hold(start)
SCL Hold(stop)
START condition
STOP condition
Figure 11-5. SCL Divider and SDA Hold
The equation used to generate the divider values from the IBFD bits is:
SCL Divider = MUL x {2 x (scl2tap + [(SCL_Tap -1) x tap2tap] + 2)}
The SDA hold delay is equal to the CPU clock period multiplied by the SDA Hold value shown in
Table 11-5. The equation used to generate the SDA Hold value from the IBFD bits is:
SDA Hold = MUL x {scl2tap + [(SDA_Tap - 1) x tap2tap] + 3}
The equation for SCL Hold values to generate the start and stop conditions from the IBFD bits is:
SCL Hold(start) = MUL x [scl2start + (SCL_Tap - 1) x tap2tap]
SCL Hold(stop) = MUL x [scl2stop + (SCL_Tap - 1) x tap2tap]
Table 11-5. IIC Divider and Hold Values (Sheet 1 of 6)
IBC[7:0]
(hex)
MUL=1
SCL Divider
(clocks)
SDA Hold
(clocks)
SCL Hold
(start)
SCL Hold
(stop)
MC3S12RG128 Data Sheet, Rev. 1.05
Freescale Semiconductor
325