MC3S12RG128 Datasheet, PDF (216/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 8 Analog-to-Digital Converter (ATD10B8CV3)
8.3 Memory Map and Register Definition
This section provides a detailed description of all registers accessible in the ATD.
8.3.1 Module Memory Map
Figure 8-2 gives an overview of all ATD registers.
NOTE
Register Address = Base Address + Address Offset, where the Base Address
is defined at the MCU level and the Address Offset is defined at the module
level.
8.3.2 Register Descriptions
This section describes in address order all the ATD registers and their individual bits.
Register
Name
0x0000
ATDCTL0
0x0001
ATDCTL1
0x0002
ATDCTL2
0x0003
ATDCTL3
0x0004
ATDCTL4
0x0005
ATDCTL5
0x0006
ATDSTAT0
0x0007
Unimplemente
d
0x0008
ATDTEST0
0x0009
ATDTEST1
Bit 7
6
R
0
0
W
R
0
ETRIGSEL
W
R
ADPU
W
AFFC
R
0
S8C
W
R
SRES8
W
SMP1
R
DJM
W
DSGN
R
0
SCF
W
R
W
5
4
3
2
1
Bit 0
0
0
0
WRAP2 WRAP1 WRAP0
0
0
0
ETRIGCH2 ETRIGCH1 ETRIGCH0
AWAI ETRIGLE ETRIGP ETRIGE ASCIE
ASCIF
S4C
S2C
S1C
FIFO
FRZ1
FRZ0
SMP0
PRS4
SCAN
MULT
ETORF FIFOR
PRS3
0
0
PRS2
CC
CC2
PRS1
CB
CC1
PRS0
CA
CC0
R
U
U
U
U
U
U
W
R
U
U
0
0
0
0
W
= Unimplemented or Reserved
Figure 8-2. ATD Register Summary (Sheet 1 of 5)
U
U
0
SC
MC3S12RG128 Data Sheet, Rev. 1.05
216
Freescale Semiconductor