MC3S12RG128 Datasheet, PDF (313/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

CLK1
CLK0
PRESCALED CLOCK
(PCLK)
INTERRUPT
Chapter 10 Enhanced Capture Timer (ECT16B8CV1) Block Description
TIMCLK (TIMER CLOCK)
4:1 MUX
CLOCK SELECT
(PAMOD)
EDGE DETECTOR
P7
8-BIT PAC3
(PACN3)
8-BIT PAC2
(PACN2)
PACA
INTERRUPT
MUX
DIVIDE BY 64
BUS CLOCK
8-BIT PAC3
(PACN1)
8-BIT PAC2
(PACN0)
PACB
DELAY COUNTER
EDGE DETECTOR
P0
Figure 10-40. 16-Bit Pulse Accumulators Block Diagram
16-BIT MAIN
TIMER
PN
EDGE
DETECTOR
DELAY
COUNTER
TCn INPUT
CAPTURE
REGISTER
SET CnF
INTERRUPT
TCnH I.C. HOLDING
HOLDING
BUFEN • LATQ • TFMOD
REGISTER
Figure 10-41. Block Diagram for Port 7 with Output Compare/Pulse Accumulator A
MC3S12RG128 Data Sheet, Rev. 1.05
Freescale Semiconductor
313