MC3S12RG128 Datasheet, PDF (105/546 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 2 Port Integration Module (PIM3RG128V1) Block Description
2.3.2.7.4 Port J Reduced Drive Register (RDRJ)
Module Base + 0x_002B
7
6
5
4
3
2
1
0
R
0
0
0
0
RDRJ7
RDRJ6
RDRJ1
RDRJ0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Read: Anytime.
Figure 2-43. Port J Reduced Drive Register (RDRJ)
Write: Anytime.
This register configures the drive strength of each port J output pin as either full or reduced. If the port is
used as input this bit is ignored.
Table 2-37. RDRJ Field Descriptions
Field
Description
7, 6, 1, 0 Reduced Drive Port J Bits
RDRJ[7:6] 0 Full drive strength at output.
RDRJ[1:0] 1 Associated pin drives at about 1/3 of the full drive strength.
2.3.2.7.5 Port J Pull Device Enable Register (PERJ)
Module Base + 0x_002C
7
6
5
4
3
2
1
0
R
0
0
0
0
PERJ7
PERJ6
PERJ1
PERJ0
W
Reset
1
1
—
—
—
—
1
1
= Unimplemented or Reserved
Read: Anytime.
Figure 2-44. Port J Pull Device Enable Register (PERJ)
Write: Anytime.
This register configures whether a pull-up or a pull-down device is activated, if the port is used as input or
as wired-OR output. This bit has no effect if the port is used as push-pull output. Out of reset a pull-up
device is enabled.
Table 2-38. PERJ Field Descriptions
Field
Description
7, 6, 1, 0 Pull Device Enable Port J Bits
PERJ[7:6] 0 Pull-up or pull-down device is disabled.
PERJ[1:0] 1 Either a pull-up or pull-down device is enabled.
MC3S12RG128 Data Sheet, Rev. 1.05
Freescale Semiconductor
105